RISC-V Comes To UECIDE

We now have the first glimmer of support for RISC-V chips in UECIDE!

If you haven't come across RISC-V yet (where have you been hiding?!) they are the most recent newcomer to the MCU and SoC block.

RISC-V is MIPS re-created from the ground up. MIPS has been with us for many many years. I myself used to use MIPS based DEC workstations back in my university days. Nowadays MIPS is in most home WiFi routers, and it's the ISA of choice for the PIC32 microcontrollers that we all love.

But RISC-V has taken MIPS back to the basics and redesigned it from the ground up to create a modern, powerful ISA. But not only that - there is one huge benefit to RISC-V over MIPS and ARM and similar ISAs: It's open source!!!

Yes, that's right: it's an open source CPU core. So not only can you use open source software on an open source development board: that development board can now have an open source SoC on it. I don't think you can get much more open than that.

So, we have been playing with the K210 from Kendryte. Which, unfortunately, is not as "open source" as RISC-V would suggest. The CPU cores (and there's two of them in there) are open source RISC-V, but the chip also contains a host of other interesting goodies that aren't open source. There's an AI coprocessor, for a start. I have no idea what that does (I know next to nothing about AI, though I have been watching Code Bullet and carykh on Youtube and have grasped some of the basic concepts, but I doubt I'd ever get around to actually trying anything). Apparently it can do realtime face recognition and such things. There's also an audio processor for doing AI-stuff with audio.

The RISC-V, though, is a dual core 64-bit RISC processor with a pair of 64-bit (double precision) FPUs. That's one FPU per core. The full list of ISA "extensions" included is:

  • I extension: Base Integer Instruction Set
  • M extension: integer multiplication and division; hardware acceleration to achieve high performance integer multiplication and division
  • A extension: atomic operations, hardware implementation of the atomic operations required by operating systems
  • C extension: compressed instructions, which can achieve higher code density and operation efficiency

And for the FPU:

  • F extension: single-precision floating point instructions
  • D extension: double-precision floating point instructions
  • Hardware single-precision and double-precision division
  • Hardware single-precision and double-precision square roots

There's also 8 MiB of SRAM, which is split between 6MiB of core RAM and 2MiB of AI RAM.

As a 144 pin BGA chip, though, it's not something just anyone can use. But there are development boards and modules available (one even including an ESP8266 for WiFi access) thanks to the guys at Sipeed. And we got a "Sipeed MAix BiT" to play with, and port the "Maixduino" core to UECIDE. The board comes pre-installed with MycroPython, but we soon deleted that. And then we took some time to do an initial port of the Maixduino core to UECIDE.

And we made it blink! Woo!